基于FPGA实现数控机床高速运动的DDA设计

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。(the source code for driving VGA and displaying the images,the testbench was offered.)

VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)

FPGA实现 DDS_讲的非常详细,师兄的一片论文-FPGA realize DDS_ talked about in great detail, of a senior thesis

RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

32-bit shifter, shifter, 32-bit.Very goog as a study file.

自己编写的，浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)

this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. -this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.