基于FPGA实现数控机床高速运动的DDA设计

讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure

code qui affiche une image sur ecran vga

IIC主设备的代码实现（verilog),从设备模型-IIC main equipment of the code (verilog), from the device model

USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

1 前大灯可以随意打开和关闭； 2 当汽车左转弯的时候，前左转向灯闪烁，同时左后灯的3盏灯由右往左闪烁； 3 当汽车有转弯的时候，前右转向灯闪烁，同时右后灯的3盏灯有左往右闪烁； 4 当汽车减速或紧急刹车的时候，左后灯和右后等同时闪烁； 5 当汽车在左转弯的同时减速，则前左转向灯闪烁，左后灯的3盏灯由右往左闪烁，同时右后灯都点亮。 6 当汽车在左转弯的同时减速，则前右转向灯闪烁，右后灯的3盏灯有左往右闪烁，同时左后灯都点亮。 -a former headlamps can be opened and closed at will; 2 when the vehicle made a left turn when the former left to lights flickered. Left lights while the three lights flashing from right-go left; 3 when the vehicle is making a turn when a right turn to the former lights flickered. Right after the lights while the three lights are blinking right and left; 4 when the vehicle deceleration or when the emergency brake, Left and right after the lights blink, and so on; 5 when the vehicle made a left turn at the same time to slow down, and then to the left before the lights flickered. Left lights three lights flashing from right-go left, right after the lights are lit. 6 when a car made a left turn at the same time to slow down, and then right before the lights to flick

挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。(Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.)

基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

网卡的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-NIC