基于FPGA实现数控机床高速运动的DDA设计

这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)

modelsim的一个非常好的教程，有程序源码，PPT，word教程-ModelSim

用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver

说明：  十进制到十六进制转换的程序。程序要求从键盘取得一个十进制数，然后把该数以十六进制的形式在屏幕上显示出来。(Decimal to hex conversion program. Procedural requirements to obtain a decimal number from the keyboard, and then the hexadecimal number to be displayed on the screen.)

16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)

xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)

LDPC的短码，码长为40速率为0.5的LDPC码的设计，用的是QC矩阵，压缩文件为原码部分，工程太大传不上去。(LDPC short code, a code length of 40 rate of 0.5 LDPC code design, using a QC matrix, the compressed file is part of the original code, do not pass up the works too.)

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)