用FPGA实现的模糊控制器 部分用VHDL编写的源程序

这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down

说明：  I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.

viterbi译码器的IP核，可以直接编译使用-viterbi decoder IP core, the compiler can directly use

用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)

数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems.

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

实验一：QuartusⅡ原理图输入法设计与实现一：实验要求    ①：用逻辑门设计实现一个半加器，仿真验证其功能，并生成新         的半加器图形模块单元。    ②：用实验一生成的半加器模块和逻辑门设计实现一个全加器，仿真验证其功能，并下载到实验板测试，要求用拨码开关设定输入信号，发光二极管显示输出信号。    ③：用3线—8线译码器和逻辑门设计实现函数F，仿真验证其功能，下载到实验板测试。要求用拨码开关 设定输入信号，发光二极管显示输出信号。二：报告内容

在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改，经设备验证无错误，且运行良好。