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8bit-cpu
VHDL由简单存储器,计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)
- 2015-10-16 14:26:34下载
- 积分:1
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MSK_BER
msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)
- 2020-11-14 11:49:42下载
- 积分:1
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基于FPGA的电子时钟设计
具体设计内容计时功能:电子表的基本功能,要求用LCD显示,显示格式是时、分、秒;校时功能:用户可以更改当前时间。设置闹钟时间:用户可以设置闹钟时间,其操作过程与校时过程一样;整点报时开关:整点报时可以由用户设定为开启或关闭两种状态,当整点报时开启时,电子表会在整点时发出1秒的闹铃声(在UP3的板上用一个LED表示);闹钟功能开关:闹钟由用户设定为开启或关闭,当闹钟开关开启时,如果当前时间与设置的闹钟时间一致,发出长达10秒的闹铃声;
- 2022-11-29 04:25:04下载
- 积分:1
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DCT_IDCT
DCT and Idct with vhdl and verilog
- 2017-11-22 17:15:12下载
- 积分:1
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通用存储器VHDL代码库,The Free IP Project VHDL Free
通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library.
-generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
- 2022-05-26 21:22:15下载
- 积分:1
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VerilogHDL,对初学者很有帮助的,可以一下的!
VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!
- 2023-02-06 11:05:03下载
- 积分:1
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MTD_MTI
(1)MTI
(2)用FFT实现MTD
(3)用FIR滤波器实现MTD
((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)
- 2020-11-04 16:39:52下载
- 积分:1
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liushui
本程序实现流水线功能,您可根据自己需要更改参数,试用芯片xilinx,用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)
- 2016-03-07 09:26:28下载
- 积分:1
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VGA控制器的VHDL,得出3条线
vga controller vhdl, it draws 3 lines -vga controller vhdl, it draws 3 lines
- 2022-01-25 16:45:25下载
- 积分:1
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sportswatch
完整的跑表设计,时,分,秒都显示,希望能对大家有用,谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)
- 2009-12-09 11:25:27下载
- 积分:1