FPGA的核心源代码，有利于学习，适合初学者…

本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.

说明：  mojo v3 complete eagle schematic

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

uart串口的vhdl语言程序。本人调试过 ，非常好用-serial UART VHDL Language Program. I debug, and very easy to use

基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera

CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频(CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion)

tms320c6747的测试程序 。用于dsp各个模块的测试，很好的例子(dsp tms320c6747)

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)