Hexadecimal to 7 segments

高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT

说明：  1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT

在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)

滤波器 Generaic FIR Filter(Generaic FIR Filter)

用Bresenham算法在FPGA上实现小数分频器，verilog编写，计算机图形法-Bresenham algorithm used in the FPGA to achieve a small number of crossovers, verilog preparation, computer graphics method

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)

基于CPLD的实现控制8x8点阵动态显示心型图案的程序，使用VHDL语言，通过调节分频系数可以实现点阵的变换速度，通过改变不同的状态可以让点阵显示不同的图案。

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

KDP晶体二倍频与三倍频；基于耦合波方程组；已于实验结果校核 (Sum Frequency in KDP)