登录
首页 » VHDL » Hexadecimal to 7 segments

Hexadecimal to 7 segments

于 2022-03-07 发布 文件大小:12.61 kB
0 116
下载积分: 2 下载次数: 1

代码说明:

Hexadecimal to 7 segments

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • verilog spi file with testbench
    verilog spi file with testbench
    2022-06-11 23:50:30下载
    积分:1
  • OFDM_TX_CR802.11-master
    OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)
    2018-11-15 17:03:03下载
    积分:1
  • Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0],...
    Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
    2022-04-13 06:40:15下载
    积分:1
  • cpu_code_8051
    vhdl code for 8051 processor
    2010-06-25 15:16:07下载
    积分:1
  • 编写 4 x 1 多路复用器使用下列方法 (1) If else 语句 (3) 具有声明 (2) Case 语句的 VHDL 代码
    编写 VHDL 代码为 4 x 1 多路复用器,使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明
    2022-02-06 00:17:34下载
    积分:1
  • FPGA控制AD7321的模块
    FPGA控制AD7321的模块,是本人亲自试验过的。有Verilog源码,和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)
    2018-01-31 20:04:27下载
    积分:1
  • A simple sequential lights
    A simple sequential lights
    2022-08-17 06:37:02下载
    积分:1
  • myAdc9248
    CycloneIV控制采样芯片AD9248-20MHz,VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)
    2017-01-31 21:55:26下载
    积分:1
  • 加法器的VHDL实现
    本资源包括了加法器的VHDL代码实现,供大家学习。
    2022-11-01 21:40:03下载
    积分:1
  • dct01
    Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)
    2011-01-17 02:40:41下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载