Hexadecimal to 7 segments

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

买的Altra公司的一款Max II EPM1270T144的电路板，其中的一个用Verilog HDL 编写的驱动数码管的程序，完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.

codic algorithm,which is used to calculate triangular functions

用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

PCI vhdl for Fpga designer to design PCI IP

Multiplexer styles in VHDL

说明：  本例的源描述超过了演示版限制的300行, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本. 联系方法: 电话:010-68912434 (The source described in this case than the demo version of the 300 line limit, if you need to be compiled with the simulation, please contact ASIC Institute of Beijing Institute of Technology to obtain the complete version of Talent system. Contact: Tel :010-68912434)

Implement LMS vhdl code.

train controler by verilog

i2c core : i2c master top