Hexadecimal to 7 segments

采用倍频及1/3、1/12倍频绘制的路面不平度频谱图（自编）(Using octave and 1/3, 1/12 octave drawn road roughness spectrum (self))

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

基于VHDL实现（7，4）汉明码的编码器和译码器(VHDL-based implementation (7,4) Hamming code encoder and decoder)

说明：  xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the description of the source file type, version of the study can not be compiled and simulation, if you need to compile this description and simulation, Beijing Polytechnic University and the Institute of ASIC link. Additionally, the cases of 75 cases with the first of a circuit with the different parts of the description, reference together two examples of this description.

说明：  biss协议源码交流 verilog hdl源码，测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.

AES算法部分模块行位移列变换以及主题程序加密解密(AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program)

DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx