加法器的VHDL实现

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)

An Alarm Project Writen in VHDL for FPGA Devices

1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)

说明：  fpga设计常用资料大全，包含常用的FPGA程序资料，对FPGA学习者有很大的帮助。(Encyclopedia of common information fpga design, FPGA that contains commonly used procedures for information on the FPGA is very useful to learners.)

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )

verilog full case and paralel case directive usage

应用背景FPGA原型的VHDL例子提供一系列清晰，易于遵循的快速代码开发模板；大量的实际例子来说明和强化的概念和设计技术；现实可实施的项目和测试在Xilinx原型板；深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。

用FPGA实现IIC通讯的主控端，最简化的代码，占用最小FPGA资源-Use FPGA to come ture the main control of the iic comunication, the most simple code and using the least FPGA resource

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )