加法器的VHDL实现

:针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给 出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片 设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.

FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)

vga 测试代码，可以显示任意彩条，棋盘，花纹(VGA test code, can display any color bar, chess board, decorative pattern )

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

verilog code for 8 bit alu

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.