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Verilog-
VHDL的基本语法,应用,建模,编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)
- 2012-03-13 19:59:29下载
- 积分:1
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FPGA正弦信号发生器
基于verilog hdl编写的FPGA正弦信号发生器,已测试。(FPGA sine signal generator)
- 2020-11-10 10:59:46下载
- 积分:1
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IIC controller for Sopc Builder
IIC控制器 for Sopc Builder-IIC controller for Sopc Builder
- 2022-05-21 02:21:43下载
- 积分:1
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fpga-jpeg
包含DCT变换,RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)
- 2013-07-02 14:10:16下载
- 积分:1
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HwLog10
用verilog写的,基于查表法实现的LOG10运算器,在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)
- 2021-04-07 15:59:01下载
- 积分:1
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VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
- 2022-02-03 20:36:30下载
- 积分:1
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VHDLquartusmodelsim
内容有VHDL语法总结及相应的实例应用,每个程序我都亲自试过,特别适合初学VHDL的同学们。常用的程序有 设计一个M序列发生器,M序列为“11110101”、 设计一个彩灯控制器,彩灯共有16个,每次顺序点亮相邻的四个彩灯,如此循环执行,循环的方向可以控制。设计一个跑马灯控制器。一共有8个彩灯,编号为LED0~LED7,点亮方式为:先从左往右顺序点亮,然后从右往左,如此循环往复等等。这些都是我在考试前熬夜总结的,很有用。如果配合开发板用的话,那就更好了
( VHDL syntax summary content and the appropriate application instance, every program I have personally tried, especially for students of beginner VHDL. Common program has designed a sequence generator M, the M series is 11110101 , a lantern controller design, a total of 16 lights, each sequence of four adjacent lights lit, so the cycle execution cycle direction can be controlled. Marquee design a controller. A total of eight lights, numbered LED0 ~ LED7, the lighting way: first left to right order of light, and then right to left, so the cycle and so on. These are all I stay up all night before the exam summary, very useful. When combined with the development board, then so much the better
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- 2016-05-15 14:51:51下载
- 积分:1
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RTC-DS1307-interfacing-with-PIC
Real time Clock DS1307 interacing with PIC using I2C.
- 2013-03-06 13:52:42下载
- 积分:1
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viterbi213
说明: 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现,包含整个QuartusII的工程文件,解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)
- 2020-12-27 21:19:02下载
- 积分:1
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mac
基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)
- 2017-04-24 10:13:55下载
- 积分:1