quartusII的环境下的基于Ep3C10144的KeyBoard程序

采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)

说明：  一种基于FPGA的调频连续波方位向多通道 FMCW SAR的实时成像信号处理方法及FPGA，包 括：步骤一、计算重构矩阵；步骤二、重构方位向 多通道数据，包括：步骤2 .1、对各个通道的回波 数据沿方位向分别间隔补零，并进行方位向傅里 叶变换；步骤2 .2、将方位向傅里叶变换之后各个 通道方位向相同位置的点组合为一个向量并与 重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA FMCW SAR real-time imaging signal processing method and FPGA, package Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation Multichannel data, including: step 2.1, echo of each channel The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out Step 2.2, after the azimuth Fourier transform The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data Step 2.3. Repeat step 2.3 for the data of different distance gates)

verilog编写的SDRAM实验，有串口调试助手和相关资料！！！！！！！！！！！！！！！！！！！！！(Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!)

JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

这是一本FPGA仿真验证的经典丛书，可以从中学习到如何编写系统的testbench,也可以是IC设计中FPGA原型验证编写系统及testbench的经典书籍。((Kluwer) Writing Testbenches Functional Verification of HDL Models.pdf)

本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

xilinx 的edk软件的应用软件开发入门 (xilinx edk)

这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" script, useful for beginners, thank you! !