VHDL数字系统设计和工程实践3，包含原理，真值表和原理图，以及VHDL源代码....

DE2-115开发板LED显示测试源码，对fpga开发者提供参考(DE2-115 development board LED display test source, provide a reference for fpga developer)

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

AES 128 bit with various device interface on FPGA

24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。(24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.)

自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)

计算多少次，把小砂轮安装数字传输比率是车轮的在一个更大完全旋转旋

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

It is Synopsys dmac controller databook

verilog coding for butterworth filter with cut off frequency with 500hz

本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband filters in which each polarization is dedicated to a selected band. The equivalent circuit is a parallel combination of two inline networks that represent each polarization. A transmission zero is generated between the two bands by properly adjusting the relative orientations of the input and output coupling apertures.)