VHDL数字系统设计和工程实践3，包含原理，真值表和原理图，以及VHDL源代码....

说明：  对fpga的学习有一点帮助，属于较为基础的部分(It has a little help to the study of FPGA, which belongs to the more basic part)

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

Verilog使用automatic function的範例(Verilog example of the use of the automatic function)

主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)

VHDL code comparator

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)

该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3

FPGA应用举例，非常适合初学者，高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo

带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

IS611v25616在NIOS II 下的驱动-NIOS II in IS611v25616 under the driver