VHDL数字系统设计和工程实践3，包含原理，真值表和原理图，以及VHDL源代码....

VGA interface using Spartan3E board from DIGILENT.Labview .vi

梁祝音乐verilog code --适用于QUATUS II 开发环境下，适合于verilog入门学员(the verilog code of liangzhu )

基于fpga的物理不可克隆函数（PUF）模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)

说明：  RS(255,247)编码解码器Verilog源代码(Verilog source code of RS (255247) codec)

FPGA AD采集八路数据，12位分辨率，小梅哥FPGA的开发程序，实测可用(FPGA AD collects eight path data, 12 bit resolution, and the development program of Mayo FPGA.)

vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.

matlab 编的瑞利信道仿真源码，对研究信道很有用(hgajdjkjhakhdkhakjlkjlka)

采用quartus的数模转换模块，RTL电路图(DAC module, RTL circuit diagram)

本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.

通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)