VHDL的四选一选择器

说明：  将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)

155B航空总线中曼彻斯特编码和译码模块，亲测可以使用，而且很好用，但是对锁相环的描述不是很仔细(155B Air bus Manchester encoding and decoding modules, pro-test can be used, and it just works)

一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển) Với bài này tôi sử dụng một nút nhất để một nút nhấn đế bắt đầu đếm dữ liệu 将重置。

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

AHB master monitor for verification

介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)

Configurable cpu core that supports Z80, 8080 and gameboy instruction sets

利用分频可以产生一系列脉冲，根据输入脉冲的不同决定你得到的一系列脉冲频率-The use of sub-band can produce a series of pulses, according to input pulse of different decisions you have a series of pulse frequency