"Verilog HDL Design Guide" 4

FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit

GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)

A program for a simple encoder using ModelSim6

在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)

说明：  matlab code for JTAG cable checking

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

HDLC接口协议的FPGA实现使用verilog-design of HDLC

基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。-Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and time.

数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)