BOOTH

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

DE0_PWM_LED_DRİ VE_Sİ MULATİ ON

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

OFDM系统新型CC编解码的verilogHDL设计，与RS编码级联，经测试误码率性能提高(OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement)

stbc空时编码源码，非常好的程序。verilog程序-STBC Space-Time Coding Source, very good program. Verilog program

VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了，下来，停止 （Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên，xuống và dừng lại）

ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD

offset_cancellation code for matlab to hdl

Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license

高通滤波器的仿真（由matlab和simulink两种方法实现）源文件以及图片示例(Simulation of the high-pass filter (implemented by the two methods matlab and simulink) source files as well as images example)