CPLD / FPGA解码器RS（204188）of the Verilog程序

4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)

基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

本文分析了当前国内外出租车计费系统的基本组成和工作原理及主要的两种设计方式:基于单片机的设计方式和基于FPGA的设计方式；并对这两种实现方式的优点和缺点进行分析，比较后确定本系统的方案：基于FPGA的出租车计费系统的设计。(This paper analyzes the current taxi charging system at home and abroad, working principle and basic components of two major design approach: the design methods based on single chip FPGA-based design approach and the two implementations to analyze the strengths and weaknesses, After comparing the program to determine the system: FPGA-based taxi billing system.)

设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

运用matlab实现fft变换，用于地震资料频谱分析！(FFT transform)

一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl

DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method