CPLD / FPGA解码器RS（204188）of the Verilog程序

AD9268的配置Verilog实现，程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)

Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display

AD0832 AD转换程序，功能完全通过测试，备注非常详细，KEILC编程，通用性强(AD0832 AD converter, fully functional test, notes, very detailed, KEILC programming, versatility)

程序用VHDL实现： 利用一秒定时测量频率 并且显示，范围0~-VHDL 0~

异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty

Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)

Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)

OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)

数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。(The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.)

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)