i2c bus project implementation can be used in altera verification environment

这是兼容的8051 VHDL CPU实现，应该不算侵权吧。 上帝保佑！-This is compatible CPU 8051 VHDL, it is not a tort. God bless!

quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE

verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the

数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)

system Verilog combinational logic

（1）用HDL设计一个多功能数字钟，包含以下主要功能：精确计时，时间可以24小时制或12小时制显示； （2）日历：显示年月日星期； （3）能用QuartusII软件仿真；

经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)

实现了三种乘法器，可以进行性能比较，比较有较之-multi

有关于SD卡的音频部分！希望对大家有用！-SD cards have on the audio portion! Hope useful for everyone!

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated