VGA的实现

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs

Xilinx 的DDR SDRAM控制器，用Verilog HDL描述- A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA

四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

基于FPGA的多波形发生器 基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator

对NC Verilog的基本介绍，详细的图解，非常适合初学者使用，一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料-Introduction of the hardware language modelsimse operation simulation software is to use the method of reference for the entry