VGA的实现

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document

软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit

本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)

说明：  用VHDL语言设计一个校验器，用for loop实现8位数据的偶校验，(With a for loop to achieve 8-bit data parity)

LPDDR2 SDRAM memories compliant to JEDEC JESD209-2.

远立科技FPGA培训文档,关于GFP项目的一些细节，很好的！(Yuan established FPGA technology training documentation)

bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)

说明：  sd卡的verilog代码，包含一些sd卡例程(SD card Verilog code, including some SD card routines)

包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)