VGA的实现

Verilog实现数据映射，解决CPM调制中的比特流向符号的转化(Implement of data mapping with Verilog)

VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的-write VHDL 8051 kernel, available, convenient, can be downloaded interested in the foreign website

说明：  THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例(CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample)

基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl(A Design of the A/D Convertion Control Module Based on FPGA)

基于FPGA的ip核FIR低通滤波器，实现滤波功能，简单好用(FPGA-based ip core FIR filter for filtering function, easy to use)

主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

VHDL tutorial for self studying