VGA的实现

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

可实现两个4bit补码的加法及减法，有溢出提示(adder with overflow hint)

Universal Shift Register

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)

关于硬件描述语言Verilog的135个经典实例，从易到难，对Verilog的编程有很大的帮助。(About the Verilog hardware description language 135 classic example, from easy to difficult, for Verilog programming of great help.)

huffman transform in vhdl language

LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)

IEEE1588de FPGA 程序，已测试，可直接用，方便(IEEE1588de FPGA program has been tested, can be directly used to facilitate)