LMS算法从opencourse

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

用可编程逻辑器件实现PWM波形即PWM波形发生器-Using programmable logic devices that realize PWM waveform PWM Waveform Generator

verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

说明：  SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)

该程序描述了运用FPGA 实现DDA圆弧插补运算(FPGA DDA)

QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the

本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)