《Verilog HDL 程序设计教程》2

实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

FSK信号发生器，基于VHDL语言，好用的！-FSK signal generator, based on the VHDL language, useful!

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)

quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)

鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

xilinx 开发板程序，LED灯控制程序-Xilinx development board procedures, LED lamp control procedures

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)