《Verilog HDL 程序设计教程》2

个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)

用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

连乘,乘法可以用简单的for循环，我这里用的是移位寄存器来做，而且是用来两个移位寄存器(this is a tool that function is multiplay,it use a special way to do multiplay .it will teach you the how to use labview )

介绍专用集成电路设计的一本书，很有参考价值，适合高年级本科生和研究生(Introduction ASIC design a book, a good reference for senior undergraduate and postgraduate)

说明：  Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)

I2C verilog 源代码 非常好的代码，大家可以-I2C verilog source code for a very good code, we can

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)

relative cpu design implementation