《Verilog HDL 程序设计教程》2

VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins

Fun little FPGA that plays a portion of Habanera

基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)

用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)

说明：  这是一个关于dQPSK的Matlab程序 这是一个关于dQPSK的Matlab程序 (This is a dQPSK the Matlab program This is a dQPSK the Matlab program)

FPGA实现DSP的Verilog 示例(FPGA realization of DSP-Verilog Example)

十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。