基于FPGA的乐曲发生器电路设计 附含源代码（quartersii环境下运行）...

说明：  快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)

龙芯CPU+IP+资源简介，希望大家能够了解自己开发的芯片。(Godson CPU+ IP+ Resource profile, hope that we can understand their own chips.)

VHDL implementation using mouse and monitor

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

verilog vga 图像处理(verilog vga)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)

Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

用于实现两个数相加的vhdl代码，在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler

数字电路点阵赛车，分为开始前5秒倒计时，59秒计时，赛车显示，赛道显示，失败提示，成功提示，移动控制以及总控制等8个模块。实现由3个开关控制点阵赛车在设置好的赛道中前进或左右移动。