一种接口控制板的逻辑电路设计CPLD程序。

软件式的VHDL学习工具，能帮助你更好的掌握VHDL的应用-VHDL-based software, learning tools, can help you better grasp the application of VHDL

NOR FLASH CONTROLLER

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

六层的电梯控制系统 用VHDL描述同时还附有系统仿真图形

verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

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用verilog编写的can总线控制器，包括设计参考历程和仿真程序，以及开发文档！(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming