_2FFT Algorithm

Bucknell Verilog Manual

DESCRIPTION OF FULL ADDER

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

说明：  Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency

一个sram的源码程序，它是256kbx16bit的sram-An SRAM of the source program, it is the SRAM 256kbx16bit

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

vhdl adder with two input 4-bit and output of 4 bits and carry