4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率....

fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)

VHDL参考手册，从事FPGA的好帮手，FPGA学院的终身伴侣！-VHDL Reference Manual, in FPGA a good helper, FPGA college life companion!

在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory

8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)

通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl

verilog入门基础以及简单编程介绍，verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language

计算三平动并联机构工作空间，自己编的，测试可以用(Calculation of three translation parallel mechanism)

说明：  将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)

单片机与ＦＰＧＡ的通信　 功能 :单片机控制写FPGA一字节数据 单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用) 单片机控制发送数据端口 -MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write data ports can be re-used, but also can be divided into use) SCM control to send data port