该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块...

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)

中科院VHDL学习资料，很好的东西，希望对大家有用-Chinese Academy of Sciences VHDL learning materials, a very good thing, everyone would like to be useful

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

these files are written in verilog but i am uploading in text format

这是一个时钟的VHDL的源程序，里面包含有源程序，还有工程文件对大家很有帮助-This is a clock VHDL source code, which contains the source code, as well as engineering documents helpful to everyone

基于VHDL的抢答器程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-Answer Based on the VHDL program, including complete source code, locking pin, as well as download files documents can be directly downloaded using

实现基于NIOS的 EP3C16与加速度传感器NMA7455的IIC基本通信(Realization of based on NIOS EP3C16 and acceleration sensor NMA7455 IIC of basic communication )

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)