making a simple clock using altera vhdl

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram

Verilog的135个经典设计实例.使你工作使用学习中，会有很大帮助，各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases )

本代码实现了输出移位寄存器功能，初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.

Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified

基于VHDl的2FSK调制！用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)

vhdl N-0.5分频方法设计，可以输入任意数值N，即分得到N－0.5的频率。-vhdl N- 0.5-frequency method, we can input arbitrary numerical N, namely, to be N- 0.5 frequencies.

DEMO中完成WIAGAND26/32的（EMP7128实现）协议程序源代码-DEMO completed WIAGAND26/32 (EMP achieved) agreement procedure source code

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)