design of 1-bit memory using cmos logic

fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)

（1）距离算法研究和设计； （2）采用FPGA/CPLD实现。 -(1) distance algorithm and design (2) using FPGA/CPLD implementation.

总结设计中的重点及注意的地方，常出现错误的地方等。-Summarize the design of the focus and attention of local, often the wrong place and so on.

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence

基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)

用vhdl写的-using VHDL write

基于FPGA的OFDM的实现，Verilog语言。(OFDM based on FPGA,by Verilog)

64-point FFT/IFFT processor architecture : Rrdix-SDF

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code