design of 1-bit memory using cmos logic

学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.

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说明：  此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)

Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)

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说明：  一个红外遥控，可以学习其他的红外编码，并存储记忆，并且将学习到的编码发送(An infrared remote control)

IEEE1588de FPGA 程序，已测试，可直接用，方便(IEEE1588de FPGA program has been tested, can be directly used to facilitate)

Verilog code for RS-(255,239) encoder.

uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)