The code is used to interface PC monitor with Spartan 3E for the display. if you...

一个八位的并行输入，串行输出的编码器；带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)

本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation

ethernet mac vhdl verilog basic

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

任意维数矩阵求逆的fpga实现，矩阵求逆是矩阵运算中最重要且最难实现的一种运算(fpga implementaion of matrix inverse of any dimension)

本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。(This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.)

这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference

Multiplication in Verilog code

sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master

本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicoun