基于交叉开关的路由器

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

Xilinx FPGA using leftover multipliers and block RAM

Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)

自编的64B/66B解码程序，做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助-NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful

This is an UART real time clock

FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页(MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247)

等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......

RAM控制的VHDL实现 真的很有用 -VHDL implementation of the RAM control true true useful useful