-
Verilog
基于FPGA的16QAM调制解调设计,以及仿真实现(Design of 16QAM Modulation and Demodulation Based on FPGA)
- 2021-02-19 16:29:44下载
- 积分:1
-
LaurentCPM
Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)
- 2013-08-16 01:32:40下载
- 积分:1
-
OFDM_802_11
ofdm的发射链路和接收链路的Verilog源代码,包括长短训练序列的生成,导频插入,加cp,ifft。(Source code of transmission link and reception link of OFDM)
- 2020-12-22 21:19:06下载
- 积分:1
-
网络上的芯片
设计处理最小化路由器端口五口三个端口,这样我们可以节省功耗和面积。
- 2023-04-01 01:15:04下载
- 积分:1
-
Four-controllable-counter
说明: 功能是(用Verilog语言的,内有比较详细的注释):
(1)计数器的功能是从0到9999计数,并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块).
(2)该计数器有一个1个nclr和一个adj_plus端,在控制信号的作用下(见下表),计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块.
计数器的功能表
nclr adj_minus 功 能
0 0 复位为0
0 1 递增计数
1 0 递减计数
1 1 暂停计数
(Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
- 2011-03-01 22:47:51下载
- 积分:1
-
sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分:1
-
modulationshaped
基带数字信号通过成形滤波(选用升余弦滚降函数)然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)
- 2007-10-31 15:27:18下载
- 积分:1
-
2011-diansai-E
2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列,伪随机序列,曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)
- 2012-02-23 10:11:07下载
- 积分:1
-
洗衣机verilog编程
应用背景本项目采用Verilog实现洗衣机的程序,它可以使用数字LED显示剩余时间。另外,它还可以使用不同的led_shining显示程序,它的运行了。而且我用BASYS2仿真和运行。在这个节目中,我会是有价值的使用几乎所有组件。关键技术有限状态机Verilog ;ISE熟练的状态控制
- 2022-01-27 18:55:26下载
- 积分:1
-
4-code
设计一个十进制计数器,具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)
- 2016-05-24 17:00:31下载
- 积分:1