cordic 的verilog 代码

本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)

使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)

Commponent for drivering EEPROM memory AT25320 from Avalon bus.

本源码采用verilog程序编写，用于配置锁相环LMX2531的寄存器，输出频率为1 GHz，寄存器的值已经经过验证，时钟输出频率没有问题，采用三段式状态机编写，顺带配置了一个AD器件，请读者选择重点参考。

基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)

握手程序，可以完美实现跨时钟域的数据传输(handshake and testbench，verilog HDL)

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)

图像去雾算法FPGA实现，使用xilinx Vivado开发环境(Image dehazing algorithm FPGA implementation using xilinx Vivado development environment)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.