verilog 代码

rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)

该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )

用Quartus II开发的一个十进制计数器，包括仿真波形，下载文件，是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)

Basic VHDL code to create a sine wave generator for an FPGA board.

说明：  rs485程序，毕业设计一部分，有需要的下载(code of rs485, part of graduation, you can download it if you need)

Verilog实现的同步模8计数器,含有.v代码,数字电路线网图以及下板照片

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)