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VerilogHDL
基于verilog convolutional coding
的卷积编码(verilog convolutional coding
)
- 2012-05-09 22:56:42下载
- 积分:1
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c_fir_ppt
C语言写得FIR滤波器代码,简单实用,是学习滤波器设计的好材料,附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design
)
- 2020-07-04 03:00:02下载
- 积分:1
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cpu mips
实现多周期mips
设计一个32位MIPS多周期微处理器 具有多种 算数指令:
(Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions
- 2023-03-29 18:05:04下载
- 积分:1
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emmc_cmd_interface_module
emmc控制芯片CMD命令线主机接口模块,(emmc control chip CMD command line host interface module)
- 2021-02-09 11:19:53下载
- 积分:1
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AHB_SRAM
实现AHB转SRAM接口实现,支持猝发,零等待延迟(Implementation of AHB to SRAM Interface)
- 2019-04-28 11:41:48下载
- 积分:1
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SOPC技术使用 verilog编的hello 程序
SOPC技术的fpga的实现verilog硬件描述语言,编写的在niosII 程序 采用altera芯片
- 2022-10-13 07:35:04下载
- 积分:1
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DCM_SP
数字时钟管理器,xilinx公司开发板集成时钟,实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
- 2021-02-19 09:59:44下载
- 积分:1
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pll
说明: fpga配置锁相环完整程序,使用quartus IP核,Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分:1
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ISE为开发环境,Verilog语言编写程序
以ISE为开发环境,Verilog语言编写程序。功能:FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分:1
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vsim
flii adder wave form 3
- 2015-04-27 20:02:44下载
- 积分:1