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SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)

用Verilog语言实现4位二进制同步计数器的功能(Write a program in Verilog language to implement the fouction of Four binary synchronous counters.)

基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)

基于FPGA，硬件描述语言Verilog驱动的CCD，严格按照CCD传感器件的驱动时序图驱动的，用的开发软件是quartus II，经过modelsim仿真，测试该代码完全可以使用。

基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)

Matlab - to hdl code for square root

串联型有源电力滤波器的 PSCAD仿真，能检测到谐波电压，本仿真的优势是能针对电压跌落或者升高进行自动补偿。(PSCAD simulation of Series type APF (Active Power Filter),this project can dectect the drop of voltage and compensates auomaticly.)