8阶的FIR的Verilog hdl实现

说明：  实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

the interface design of pcie based on FPGA

在FPGA中，采用verilog HDL语言实现图像处理算法sobel，仿真实验通过(In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment)

基于vhdl的pid控制器设计，可以用quartus等软件实现。数字控制系统pid设计源代码。(Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co)

说明：  altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)

Two-Dimensional Rank Order Filter Author: Gabor Szedo

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL. )