I2C 的ip核与testbench

UART program for fun(UART)

在 verilog 代码 sdram 控制器. 在 first.rar-- matlab 代码是在 first.rar 为接收器分布给出了在 MATLAB 文件 clockTreeAssignment.m 中找到零偏差时钟直线树。 发现从根源到汇的延迟 （时钟延迟）。使用埃尔莫尔延迟-model(i.e no need to do SPICE simulation) 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

Multiplication in Verilog code

EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals. )

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

设计一个哈夫曼编码器 要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。 ① 组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。 ② 输入数据序列的长度为256。 ③ 先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Designing a Huffman Encoder Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element. (1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001. (2) The length of the input data sequence is 256. (3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence.)

测温，数码管显示，基于FPGA 的verilog程序，基于DS18B20(Temperature measurement)

说明：  OFDM的简易verilog仿真程序，环境是quartus，版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)

Link the VGA adapter located in the altera DE2board to a monitor

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题(Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging)