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JOP of RAM VHDL source code, classic classics, difficult to find a good price.
JOP的RAM VHDL源码,经典的经典,不易找到的好东东,-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
- 2022-10-01 16:00:03下载
- 积分:1
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xapp524
xilinx FPGA 与高速ADC LVDS接口的范例程序(xilinx FPGA ADC LVDS interface)
- 2021-02-05 17:29:57下载
- 积分:1
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table-for-sin-functionof-
DDS中的正余弦生成,初始相位相差90度,可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)
- 2013-12-17 22:09:56下载
- 积分:1
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watch
数字钟,简单的数电应用,电子表源程序,常用也使用-watch
- 2022-04-18 14:17:50下载
- 积分:1
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先进先出
第一次输入和输出第一缓冲 vhdl 代码
- 2023-02-16 13:20:04下载
- 积分:1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分:1
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VHDL实现SPI接口转I2c接口的源代码,可以直接调用
VHDL实现SPI接口转I2c接口的源代码,可以直接调用-VHDL realize I2C interface SPI interface to the source code, you can directly call
- 2023-03-01 17:50:04下载
- 积分:1
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This procedure to design an FPGA
本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定,激磁方式设定和定位角度的换算等工作,后一个模块用于对换算后的角度量编码输出。-This procedure to design an FPGA-based 4-phase stepper motor positioning control system. Direction set by the stepper motor circuit module, stepper motor stepper movement and positioning control module and the code output modules. The first two modules complete the motor rotation direction setting, exciting way of setting the angle and positioning of the conversion work, after a module for the point of view of the volume of converted output encoding.
- 2022-05-09 09:25:30下载
- 积分:1
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fpga_dk_ps2_vga
ps2 vga interface in vhdl code
- 2011-11-08 11:09:35下载
- 积分:1
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通过VHDL语言的例子,通过乒乓球运动FPGA原型楚原型(1章)
应用背景FPGA原型的VHDL例子提供一系列清晰,易于遵循的快速代码开发模板;大量的实际例子来说明和强化的概念和设计技术;现实可实施的项目和测试在Xilinx原型板;深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-03-18 13:19:49下载
- 积分:1