CPU代码

用verilog写的很好的cpu core-using Verilog write a good cpu core

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)

鼎lpc1788尚开发板的vga的显示，1024x768(lpc1788board,lcd to vga display,1024x768)

说明：  激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)

RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine

vhdl code for counterand detemines how counter works

使用FPGA实现UART收发。支持多种波特率。(Using FPGA to achieve UART transceiver.)

完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.

一位LED显示的VHDL程序，挺简单的，买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone