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SIREN
An Alarm Project Writen in VHDL for FPGA Devices
- 2010-10-01 16:37:48下载
- 积分:1
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xapp224_data_recovery_design-file
XAPP224 VHDL Data Recovery design file
- 2021-03-30 17:49:09下载
- 积分:1
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ref-sdr-sdram-verilog
sdram控制器的开发程序,还有文档,可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)
- 2008-06-13 22:15:41下载
- 积分:1
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clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分:1
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介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进
制码转换成8421BCD 码的原理、设计思路和软件实现。...
介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进
制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera
- 2022-02-16 07:54:31下载
- 积分:1
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是vhdl语言,在fpga开发板上实现十进制技术(7段数码管显示),包括复位,清零,计数使能。...
是vhdl语言,在fpga开发板上实现十进制技术(7段数码管显示),包括复位,清零,计数使能。-Is the VHDL language, in the FPGA development board realize decimal technology (7 digital tube display), including reset, cleared, counting enable.
- 2022-03-20 12:25:41下载
- 积分:1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分:1
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quartus2
quartus2的中文文档,不是很全,仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)
- 2010-07-29 19:49:52下载
- 积分:1
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polar_encoder_1024 (1)
该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)
- 2021-01-10 16:58:50下载
- 积分:1
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VHDL38decoder
VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)
- 2020-06-29 23:40:03下载
- 积分:1