这是一个GPIB源程序代码,里面有硬件相对应的代码

小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)

code qui affiche une image sur ecran vga

基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)

cpld下在线资料ByteBlaster-CPLD under the online information ByteBlaster

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)

The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E

表决器，简单实现了表决功能，无显示功能 -vote

说明：  SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

北航夏宇闻的Verilog的PPT讲稿，挺经典的，适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)