为验证系统的Verilog设计

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

说明：  以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

AES128 encription vhdl code

一些例子程序需要的话可以下来看看新手推荐-Some examples of procedures can be down if necessary to see novice Recommended

实现spi接口的传输，并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data

四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.

青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err

The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below:   tl   - HDL design files   sim   - simulation files   synth - Synthesis related files   par   - Place/Route related files 以及DDR SDRAM控制器设置.pdf文件

基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)

基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)