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interpolator
说明: 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现(Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of)
- 2008-10-21 12:49:38下载
- 积分:1
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vhdl 数字时钟设计
资源描述
VHDL语言是一种用于电路设计的高级语言。它在80年代的后期出现。最初是由美国国防部开发出来供美军用来提高设计的可靠性和缩减开发周期的一种使用范围较小的设计语言
现在利用vhdl语言,通过原件例化语句,来编写一个数字时钟
- 2022-02-15 16:13:59下载
- 积分:1
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canbus verilog实现,原代码文件
canbus verilog实现,原代码文件-canbus verilog implementation, the original source document
- 2022-06-15 18:20:23下载
- 积分:1
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fenpinqi de vhdlchengxu gongnengfnagzhen,政
分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
- 2022-02-21 21:03:34下载
- 积分:1
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cordic_verilog
cordic算法的verilog 语言实现,注释详细,资料齐全,实现了cordic算法的各个功能,可以计算正余弦(cordic algorithm verilog language, detailed notes, and complete information)
- 2020-06-29 16:20:02下载
- 积分:1
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verilog编写的全功能串口
verilog编写的全功能串口-verilog programme of serial port
- 2022-05-19 04:03:59下载
- 积分:1
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Verilog语言编写的电话计费系统,这只是源代码,需要在quartusII等软件下运用...
Verilog语言编写的电话计费系统,这只是源代码,需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII
- 2023-01-23 23:25:03下载
- 积分:1
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rs232_receiver
RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)
- 2009-07-06 19:56:52下载
- 积分:1
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1
说明: VGA图像显示,可实现图片和实现移动功能(VGA image display, enabling images and moving functions to achieve)
- 2014-07-03 11:17:12下载
- 积分:1
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greedy_snake
基于Basys2开发板实现VGA输出,PS/2键盘接入的贪吃蛇游戏,键盘上下左右控制方向,小键盘+键控制速度,小键盘回车开始游戏,空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)
- 2021-03-27 17:09:12下载
- 积分:1