很多实用的例程，包括触发器，译码器，多路选择器

FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)

RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

codic algorithm,which is used to calculate triangular functions

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)

Mano s cpu for Man s instructions

morris mano basic vhdl code in ise

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)