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GPS
在fpga中对GPS信息采集程序。具有很好的参考性(In the fpga in the GPS information collection procedures. Has a very good reference)
- 2011-11-17 13:49:20下载
- 积分:1
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四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D...
四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
- 2023-04-13 16:10:03下载
- 积分:1
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ADC_TCL5510-verilog
verilog 驱动TLC5510代码,TLC5510是高速的AD,可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)
- 2020-08-13 21:28:29下载
- 积分:1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
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ed2_prac5_conta_finfin
program in hdl that this open mind in digital resources
- 2009-06-27 08:08:08下载
- 积分:1
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ADC实验
基于stm32开发平台的,模拟ad采样程序设计,可直接下载使用(stm32 zhijiexiazaishiyong)
- 2018-02-02 00:32:43下载
- 积分:1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分:1
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布斯算法结构的 VHDL 代码
布斯算法用于在计算机体系结构的两个二进制现在的乘法。随着处理器为转移的运行情况良好,不能轻易做乘法这就是为什么正在使用它。
- 2022-08-08 00:31:29下载
- 积分:1
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一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考...
一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
- 2022-01-31 04:35:55下载
- 积分:1
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RS码译码器
采用VHDL语言实现基于BM算法的RS译码器,附件为整个工程文件,内附波形仿真图。程序在QUARTUS II 9.0下仿真通过
- 2022-06-03 16:19:45下载
- 积分:1