浅显易懂的vrilogHDL的程序，可以帮助你迅速上手

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

基于FPGA的多功能电子时钟的设计很经典的哦-FPGA-based multi-functional electronic clock designs are very classic Oh

主要介绍了关于MAGIC3000系列CPLD开发板的十个实例,如霓虹灯演示、与PC串口通信等。-Mainly on the introduction MAGIC3000 series CPLD development board of the 10 examples, such as neon demonstration, with the PC serial port communications.

4*4按键扫描电路，用数码管显示0~F，基于VHDL语言设计，包括按键扫描，数码管扫描，数码管显示，按键消抖等代码

verilog code for apb to ahb convert

Frecuencymeter digital, clk frequency 10 MHZ, exhibition in 7 segments

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

matlab bpsk with rayleigh performance expirement