浅显易懂的vrilogHDL的程序，可以帮助你迅速上手

SHA256加密过程,非常详细，内附原码，还有文档，很可用~(SHA256 encryption process, very detailed, containing the original code, as well as documents, it is available ~)

简易环形FIFO的设计、简单异步串行通信接口设计等-verilog

C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)

FIFO的verilog描述(Verilog description of the FIFO)

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS

32 bit RISC Processor with 3 stage pipeline

使用Verilog实现的AD采样，很有用的！(Implemented using Verilog AD sampling, very useful!)