浅显易懂的vrilogHDL的程序，可以帮助你迅速上手

cpld下在线资料ByteBlaster-CPLD under the online information ByteBlaster

这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction

FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit

synopsys的主要的工具介绍，包括DC,PT,Formality等，对于初学IC设计者了解设计工具有很大帮助。(synopsys of the main tools for presentations, including DC, PT, Formality, etc., for the beginner tool for IC designers to understand the design of much help.)

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

用FPGA实现pwm调制波，通过单片机软核控制输入量来实现任意占空比方波的产生-wave

USB口的设计，包括驱动程序的设计，以及软件的安装演示，软件的介绍，以及工作模式-USB port design, including the driver design, and installation of software, presentation, software presentation, and working models

基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0

VHDL实例这是我下载到的最好的VHDL实例，看完这些实例，可以使你有一个长足的进展-VHDL example