模数转换的一个工程

codes for zynq devices

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.

集成电路的规模日益扩大

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)

利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用-Realize the frequency of testing the use of FPGA-based VHDL realize, has a good test performance can be directly used

VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure

基于fpga和51单片机的等精度频率计，通过fpga对信号进行采集，数据传给单片机计算，再由12864进行显示，可进行频率，周期，脉宽，占空比，幅值等的测量。(Fpga and 51 microcontroller based precision frequency meter, through fpga for signal acquisition, data to the microcontroller to calculate, and then by 12864 for display, can be measured frequency, period, pulse width, duty cycle, the amplitude and the like.)

王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)