4：2优先编码器的VHDL代码

一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

本文详细介绍了我们的电气工程项目；

说明：  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source

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电子密码锁程序，密码输入正确之后，锁就打开，如果输入的三次的密码不正确，就锁定按键3秒钟，同时发现报警声-Electronic code lock procedure, enter the correct password, the lock will open, if entered incorrect password three times, on the lock button 3 seconds, also found the sound alarm

FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)