fpga 基于FPGA的mif文件创建与使用

It is the FSM implemented in Xylinx 14.7 on FPGA

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

十进制计算机，实现十进制计数功能，简单可靠(vhdl)

VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners

verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the

Quartus ii 入门基础 仅针对初学者 望各位童鞋们指导 呵呵 (Quartus ii entry basis only for beginners looking to guide their children' s shoes Oh you)

cadence verilog lanaguage and simulation course

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)