利用fpga实现的DDS，可输出正弦波，输出频率可调

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

REEDSOLOMON source code

ISA总线资料《ISA System Architecture》(ISA System Architecture)

这是一篇现代通信原理课程的作业报告.题目为几种时频分析方法比较及应用.详细介绍了短时傅里叶变换、小波变换、魏格纳—威利分布和Cohen类时频分布这4种典型时频分析方法,并作了比较(This is a modern communication Principle operating report. Entitled Comparison of several time-frequency analysis and 应用. 详细 Jieshao the short time Fourier transform, wavelet transform, Wigner- Willie distribution and frequency distribution of Cohen Lei This four kinds of typical time-frequency analysis method, and compared)

papers based on distributed arithmetic.

FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )

VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)