IS611v25616在NIOS II 下的驱动

cpld 控制 8-32M sdram 控制器 maxII epm570实现。 pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation

VHDL Bible. It is a must read for any front end vlsi designer.

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

说明：  1、SignalTap II Logic Analyzer使用方法； 2、掌握捕获条件的设置 3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer; 2. Master the setting of capture conditions 3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)

使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0―99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求-The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requirement through

FPGA核心代码，可在工程中直接使用。-FPGA core code, can be directly used in engineering.

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)

说明：  OFDM基带处理的书籍和论文，以及发送和接收端源码。(OFDM baseband processing books and papers, as well as send and receive source code.)

关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)