I2C Bus Controller ALTERA the VHDL source code

verilog入门基础以及简单编程介绍，verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

说明：  按键消抖,避免按键抖动造成信号误触发，增大按键输入的可靠性(Key jitter elimination, avoid key jitter caused by signal error trigger, increase the reliability of key input)

是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.

说明：  使用verilog实现ppm解码器，功能仿真通过，附设计说明，THU微纳电子系ic设计课大作业。(a ppm decoder written in VerilogHDL, a design document is available)

上海交通大学电子信息与电气工程学院VHDL经典教程-Shanghai Jiaotong University Electronic Information and Electrical Engineering, Institute of Classical VHDL Tutorial

4 seg display, button debouncer, and controller for parking meter

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

说明：  credit base network on chip(network on chip (noc))

ＦＰＧＡ与ＳＤＲＡＭ　的　ＶＨＤＬ　接口设计(ｔｈｅ　interface of FPGA and SDRAM)