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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分:1
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08EE06EDA 实验 4(VHDL 状态机设计_序列检测器)6/7/2008
08EE06EDA 实验 4(VHDL 状态机设计_序列检测器)6/7/2008-design thesis requirement by vhdl
- 2022-03-29 09:41:25下载
- 积分:1
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lab6
说明: 使用vivado和Xilinx开发板实现VGA图像显示,开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)
- 2020-12-08 13:10:53下载
- 积分:1
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elpiano
自己写的FPGA实现电子琴的VHDL程序,曲目是两只老虎,用到一些模块,和片内存储间,呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)
- 2020-12-28 01:39:02下载
- 积分:1
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Design and Implementation of the SNMP Agents
A programming language that can decode alpha numeric
- 2018-12-06 10:15:01下载
- 积分:1
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vhdl_quick-learn
vhdl learnig material............
- 2015-08-07 19:09:24下载
- 积分:1
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chengxu_jieshou
nrf24l01发送代码,verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)
- 2017-08-09 19:04:16下载
- 积分:1
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ADC0832
AD0832 AD转换程序,功能完全通过测试,备注非常详细,KEILC编程,通用性强(AD0832 AD converter, fully functional test, notes, very detailed, KEILC programming, versatility)
- 2011-09-01 17:20:08下载
- 积分:1
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This procedure for the serial communication procedures, the use of Verilog langu...
此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.
- 2022-04-22 21:51:37下载
- 积分:1
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generic_dpram
IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY
- 2013-09-30 19:03:40下载
- 积分:1