A basic SDH transmission module STM

基于VHDL语言编写，可下载到FPGA板子上实现的cordic算法实现的设计，并用该算法实现sin和cos的计算，计算结果显示在数码显示管上，已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)

说明：  Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)

vhdl code for fir filter

说明：  基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

说明：  秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)

verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)

用vhdl编写的简易电子中设计，经过测试成功，且用记事本上载，无需阅读器进行阅读。-Use of VHDL in the preparation of simple electronic design, has been tested successfully, and use Notepad to upload without reader reading.

基于FPGA的1553B总线编码解码器的设计-1553B Bus FPGA-based codec design