-
Complete-RAM
ram 64KB designed by haneesh in verilog
- 2011-07-15 00:57:01下载
- 积分:1
-
一个8位CISC结构的精简CPU,2还提供了编译器
一个8位CISC结构的精简CPU,2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分:1
-
clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分:1
-
Altera_Audio
针对Altera的DE2/ DE1交互板的音频核心的音频编解码器(编码器/解码器),并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and output.)
- 2015-04-01 22:21:49下载
- 积分:1
-
FIFO
FIFO的VERILOG代码编写
可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)
- 2010-10-11 20:35:47下载
- 积分:1
-
scope_VGA
利用IIC接口的4路 ADC max1037,采集思路信号,通过在FPGA内部的构建DeltaSigma DAC软核,在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)
- 2012-07-24 00:41:29下载
- 积分:1
-
tdma_code
tdma参数化模块。可以自动生成2的n次的tdma哥时隙,用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)
- 2013-09-03 21:52:51下载
- 积分:1
-
EDA常用计数函数VHDL程序设计,减法计数器:可预置数:
EDA常用计数函数VHDL程序设计,减法计数器:可预置数:-common counting function EDA VHDL programming, subtraction counter : Preset :
- 2022-03-25 01:33:15下载
- 积分:1
-
TCL2543
基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换(The TLC2543 controller based on FPGA, using state control of ADC conversion)
- 2020-11-18 15:59:39下载
- 积分:1
-
dds_ok1
说明: 基于FPGA的信号发生器,产生了正弦波,方波,锯齿波和三角波四种波形,按下一次按钮,波形切换一次。按下另一个按钮,改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)
- 2020-09-16 18:30:37下载
- 积分:1