图书馆的IEEE

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

reed-solomon译码器。共有7个文件，分别为译码器的7个模块。-reed-solomon decoder. A total of seven papers, respectively, the decoder module 7.

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code

veriloghdl语言熟练的一个很好的cpu代码

说明：  使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

ldpc编解码程序。有testbentch。-ldpc encoding and decoding process. There testbentch.

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning