parallel adder

Implementation of Image Processing Algorithms in FPGA Hardware.

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）(communication control used in pulse width detection procedures, VHDL modular organization to achieve (original))

Dynamic Power Management for the Iterative Decoding of Turbo Codes

GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF

rc6 algorithm designed based on verilog and is verified

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)