parallel adder

VHDL operators basics

计算多少次，把小砂轮安装数字传输比率是车轮的在一个更大完全旋转旋

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

说明：  SHA-1加密算法的IP核，内涵文档，仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

电子时钟VHDL程序与仿真的vhdl源代码-Electronic clock and simulation of VHDL procedures vhdl source code

介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料-Introduction of the hardware language modelsimse operation simulation software is to use the method of reference for the entry

该源码表述了ecc算法如何用vhdl实现RSA（Ron Rivest，Adi Shamir，Len Adleman三位天才的名字）一样，ECC（Elliptic Curves Cryptography，椭圆曲线密码编码学）也属于公开密钥算

说明：  利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)

four bit counter verlog source code for veriwell including test bench