一个可用的很不错的DDS 频率合成程序，用VHDL语言编写

基于EPM1270的VGA显示器接口源码Verilog-Based on the EPM1270

可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)

说明：  鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

these files are written in verilog but i am uploading in text format

des code source vhdl sur fpga

在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files

说明：  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

本资料中有100个vhdl的例子，是很好的学习参考资料。对于学习vhdl的人来说是很有用的。-This information has 100 vhdl example, is a good learning reference. For those who learn vhdl is very useful.

ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)

说明：  基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)