Elevator designed to control the lift design 6 original VHDL language

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

说明：  bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

四分频的程序，输出clkout0就是二分频，clkout1是四分频-Quarter-frequency process, the output clkout0 is two-way, clkout1-fourth the frequency

等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)

多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

说明：  there's a clock divider for DE2 altra board clock (50MHz)

This file contains async fifo design

this a test keyboard code -this is a test keyboard code

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题(Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging)