Elevator designed to control the lift design 6 original VHDL language

cic_dec_8_three CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL

这是使用systemgenerator的一个入门程序和范例使用matlab和system generator共同实现，并配有教学文档，清晰简单，易懂(This is an entry using systemgenerator procedures and examples using matlab and the system generator together to achieve, and with a teaching document, clear and simple and easy to understand)

verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )

此代码是加密实现在 vhdl。在加密、 RC6 (Rivest Cipher 6) 是一种对称密钥 块密码从RC5派生。它是由Ron Rivest、马特 Robshaw、 雷西德尼和益群丽莎贤以满足高级加密标准(AES)竞争的要求设计的。该算法是一个五个入围者，和也提交给湖怪兽和CRYPTREC项目。它是一种专有

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

这一计划表明它是如何在如此逻辑门是门NAND，什么它NAND它是结合两个闸门之一，并没有。

verilog code for bus controller

altera嵌入式设计大赛文章，车载cots设计实现-Embedded Design Contest altera article, cots Car Design

用Verilog语言实现汉明编码，很粗燥，是大三的时候做的(With the Verilog language Hamming code, it is rough dry, a junior at the time to do)