用 vhdl 实现的 nand 闪存

verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)

包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)

关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助-DIVIDE

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)

VHDL 2008 A reference book on VHDL-VHDL 2008 A reference book on VHDL

一个简单的微处理器的实现，能够进行几种常见的操作，对于熟悉计算机的工作原理很有帮助，并且附有详细的设计报告和设计思路。在word文档最后给出了源代码。-a simple microprocessor to achieve, for several common to the operation of the computer for those familiar with the working principle helpful, and with the detailed design reports and design ideas. The word is the final document source code.

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)