verilog hdl coding DDR sdram control for fpga

考研复试口语，适合计算机专业考研复试口语专业课(Traditional Interview spoken, spoken for Specialized Computer Traditional Interview)

Program to implement convolution of two signals.

Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.

实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL

Use full for knowing board details while making projects on FPGA and matlab simulations

利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.

VCP201_CODE is a FPGA source code.

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)

电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code

DE2-70开发板中附带的控制面板，可以读取存储器中的数据，这个可以正常连接和读取，有好几版本的，有的不能用，而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)