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Interleaver_Deinterleaver
通信中卷积交织/解交织FPGA源程序,采用verilogHDL代码实现,包含测试程序,经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)
- 2021-04-17 15:18:53下载
- 积分:1
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mybch1
说明: 实现(7,4)BCH码的编码和译码。已知生成矩阵和校验矩阵,通过c=m*G进行编码,译码时利用伴随式译码。s=c*H‘,求得伴随式,对应的错误图样找到错误位置,对错误位置进行更正,得到译码结果。(Coding and decoding of (7,4) BCH Codes)
- 2021-04-27 17:28:44下载
- 积分:1
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AD
说明: FPGA控制AD7321的模块,是本人亲自试验过的。有Verilog源码,和简单文档。(FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.)
- 2009-08-18 20:31:53下载
- 积分:1
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基于FPGA的uart控制器,波特率可选,VHDL编程,Quartusii 6.0 平台,vhdl语言编程...
基于FPGA的uart控制器,波特率可选,VHDL编程,Quartusii 6.0 平台,vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
- 2022-12-05 20:10:10下载
- 积分:1
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rgb2yuv
用VHDL和verilog编写的RGB颜色空间到YUV颜色空间的转换程序, 是FPGA视频处理中的常用程序!(Written in VHDL and verilog using RGB color space to YUV color space conversion process is commonly used in video processing FPGA program!)
- 2010-06-08 22:15:01下载
- 积分:1
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Verilog HDL language proficiency of a good cpu code
veriloghdl语言熟练的一个很好的cpu代码
- 2022-10-31 00:00:03下载
- 积分:1
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Double_Pulse_Test
利用VHDL语言描述出一个双脉冲,可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)
- 2020-11-22 12:29:35下载
- 积分:1
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LPC1788_VGA_COLOR
鼎lpc1788尚开发板的vga的显示,1024x768(lpc1788board,lcd to vga display,1024x768)
- 2014-12-15 13:34:06下载
- 积分:1
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RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
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简易制作呼吸灯小程序
主要通过频率分配 实现不同时间的变化 达到呼吸一闪一闪的效果
- 2022-07-10 13:56:48下载
- 积分:1