FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第四个文档...

ANALYSIS OF ALL GATESS

流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!

用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)

复旦cpu COS

Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.

lap of altera . it s basic about verilog

卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve

用Quartus II开发的一个十进制计数器，包括仿真波形，下载文件，是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)

用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)

我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh